ADC and DAC Systems

BAE SYSTEMS ATC provides specialised design skills for both analogue to digital conversion (ADC) and digital to analogue conversion (DAC) based subsystems.

In house test facilities are available to determine parameters for both ADC and DAC performance. For example spurious free dynamic range (SFDR), effective number of bits (ENOB), integral and differential non-linearity.
The transition between the analogue signal domain to the digital domain, and vice versa, are common requirements in current electronic equipment. The analogue engineer will perform; noise figure analysis, frequency planning, third order intercept point calculations, mixer product calculations, compression point analysis, and spurious free dynamic range calculations for the analogue section. The digital engineer will calculate; effective noise bandwidths, data growth, window weighting loss, probability of detection, signal to noise ratio and threshold calculations. The ADC or DAC are often seen as just an interface between the two domains. Consequently the system effects of data conversion are often neglected with significant performance loss on that which could be achieved. For instance the data conversion process impacts on system noise figure. This is illustrated in the following example.
The theoretical dynamic range (DR) of an ADC or DAC is often quoted as 

(1)

Equation 1 gives the maximum theoretical dynamic range for an ADC or DAC with N bits. The noise floor due to quantisation is 6.02N+1.76dBs below full scale. For a simple receiver system with a 1dB noise figure lets assume the receiver’s noise floor is equal to the theoretical ADC’s quantisation noise floor. The noise coming out of the ADC is now the combined ADC and receiver noise and is thus 3dB higher than the analogue receiver noise floor input to the ADC. The system noise figure has gone from 1 dB to 4 dB. The conclusion is that the receiver’s noise floor has to dominate the ADC’s noise floor. With a the receiver’s noise 10dBs above the ADCs noise floor the noise figure is degraded from 1 dB to 1.4 dB. The theoretical dynamic range now becomes

(2)

Where the input noise has been set 10 dB above the ADC’s noise floor and the ADC noise contributes 0.4 dB increase in the signals output noise floor. A lower contribution to the noise figure could be achieved, but at the expense of a greater loss in dynamic range.
In the real world the actual ADC or DAC performance is always less than the theoretical figures and it is necessary to set the receiver’s noise 10 dB above the actual ADC’s noise. When the noise figure contribution is combined with other ADC and/or DAC limitations; slew rate, aperture jitter, feed through it becomes apparent that specialised skills are required to design such subsystems to obtain maximum performance.

Circuit Layout

The management of circuit layout is crucial to optimum performance. The need for digital, analogue, and safety grounds in conversion circuits can result in ground loops that significantly degrade converter performance. A design that works for a single converter will often fail when multiple converters are used in a system due to ground loops.

Performance Extension

ADC and DAC performance can be extended by the use of ‘dither’ techniques where noise is injected to randomise the conversion error. Additionally techniques of over sampling and under sampling can be used. To extend the frequency of operation other Nyquist zones can be used as in the 1 GHz Radar Waveform Generator below where the analogue output is in the 550 to 950 MHz band though the DAC clock rate is 1 GHz.